Fast Fault Emulation for Synchronous Sequential Circuits

Current paper presents an approach to emulate fault simulation of sequential circuits on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. In the paper, we explain the problems associated to fault emulation for sequential circuits. Two alternative approaches are described, which can be considered as trade-offs in terms of required FPGA resources and fault grading accuracy. In addition, an environment for reconfigurable hardware emulation of fault simulation is proposed. Experiments show that it is beneficial to use emulation for circuits/methods that require large numbers of test vectors, e.g. simulation-based test pattern generation or validation.